Abstract
With the conventional directed testbench, it is highly improbably to handle verification of current complex Integrated Circuit (IC) designs, because a person has to manually create every test case. The greater the complexity of the designs, the higher the probability of bugs appearing in the code. Increasing complexity of ICs has created a necessity for performing verification on designs with an advanced, automated verification environment. Ideally this would eliminate chip re-spins, minimizing the time required to enable checking of all the design specifications, ensuring 100% functional coverage. This paper deals with the design of Synchronous FIFO using Verilog. A FIFO (First-In-First-Out) is a memory queue, which controls the data flow between two modules. It has control logic embedded with it, which efficiently manages read and write operations. It has the capability to notify the concerned modules regarding its empty status and full status to help ensure no underflow or overflow of data. This FIFO design is classified as synchronous, as clocks control the read and write operations. Both read and write operations happen simultaneously using of Dual port RAM or an array of flip-flops in the design. After designing the Synchronous FIFO, its verification is carried out using the Universal Verification Methodology (UVM). A detailed discussion about the verification plan and test results is included.
Publication Date
12-2018
Document Type
Master's Project
Student Type
Graduate
Degree Name
Electrical Engineering (MS)
Department, Program, or Center
Electrical Engineering (KGCOE)
Advisor
Mark A. Indovina
Advisor/Committee Member
Sohail A. Dianat
Recommended Citation
Nagarajan, Vinoth, "The Design and Verification of a Synchronous First-In First-Out (FIFO) Module Using System Verilog Based Universal Verification Methodology (UVM)" (2018). Thesis. Rochester Institute of Technology. Accessed from
https://repository.rit.edu/theses/9980
Campus
RIT – Main Campus
