Abstract

The role of amorphous IGZO (Indium Gallium Zinc Oxide) in Thin Film Transistors (TFT) has found its application in emerging display technologies such as active matrix liquid crystal display (LCD) and active matrix organic light-emitting diode (AMOLED) due to factors such as high mobility 10-20 cm2/(V.s), low subthreshold swing (~120mV/dec), overall material stability and ease of fabrication. However, prolonged application of gate bias on the TFT results in deterioration of I-V characteristics such as sub-threshold distortion and a distinct shift in threshold voltage. Both positive-bias and negative-bias affects have been investigated. In most cases positive-stress was found to have negligible influence on device characteristics, however a stress induced trap state was evident in certain cases. Negative stress demonstrated a pronounced influence by donor like interface traps, with significant transfer characteristics shift that was reversible over a period of time at room temperature. It was also found that the reversible mechanism to pre-stress conditions was accelerated when samples were subjected to cryogenic temperature (77 K). To improve device performance BG devices were subjected to extended anneals and encapsulated with ALD alumina. These devices were found to have excellent resistance to bias stress. Double gate devices that were subjected to extended anneals and alumina capping revealed similar results with better electrostatics compared to BG devices. The cause and effect of bias stress and its reversible mechanisms on IGZO TFTs has been studied and explained with supporting models.

Library of Congress Subject Headings

Thin film transistors--Materials; Thin film transistors--Electric properties; Thin film transistors--Testing

Publication Date

12-20-2018

Document Type

Thesis

Student Type

Graduate

Degree Name

Microelectronic Engineering (MS)

Department, Program, or Center

Microelectronic Engineering (KGCOE)

Advisor

Karl D. Hirschman

Advisor/Committee Member

Michael Jackson

Advisor/Committee Member

Robert Pearson

Campus

RIT – Main Campus

Plan Codes

MCEE-MS

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