Abstract

A proposed process flow for a complete FinFET etch module is presented as well as experiments to ensure that the target films are etched uniformly with proper rate, selectivity and anisotropy. The proposed process flow was developed at RIT, designed to closely reproduce what the semiconductor industry uses for a Self-Aligned Double Patterning (SADP) process module while advancing RIT's current cleanroom facility capabilities.

The etching experiment is proposed such that a sufficient degree of etch endpoint control can be achieved without a spectrophotometer for endpoint detection using the Magnetically Enhanced Reactive Ion Etching (MERIE) system at RIT. Without the proper etch data a number of critical steps would be incredibly difficult to control. Prior to this work across wafer etch non-uniformity was reported to be approximately 10% with a regular rate of 1400-1500A/min. This was improved through various means to a nonuniformity of < 1% and a rate of 2200A/min on average. A way to achieve the mandrel etch and strip using gas ratios of 4:2:1::CF4:CHF3:C2F6 and 4:1::CHF3:C2F6, was derived, respectively.

Library of Congress Subject Headings

Semiconductors--Etching; Field-effect transistors--Design and construction; Thin films

Publication Date

10-19-2018

Document Type

Thesis

Student Type

Graduate

Degree Name

Microelectronic Engineering (MS)

Department, Program, or Center

Microelectronic Engineering (KGCOE)

Advisor

Robert Pearson

Advisor/Committee Member

Karl Hirschman

Advisor/Committee Member

Michael Jackson

Campus

RIT – Main Campus

Plan Codes

MCEE-MS

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