Research in recent years has demonstrated that intra and inter-chip wireless interconnects are capable of establishing energy-efficient data communications within as well as between multiple chips. This thesis introduces a circuit level design of a source degenerated two stage common source low noise amplifier suitable for such wireless interconnects in 45-nm CMOS process. The design consists of a simple two-stage common source structure based Low Noise Amplifier (LNA) to boost the degraded received signal. Operating at 60GHz, the proposed low noise amplifier consumes only 4.88 mW active power from a 1V supply while providing 17.2 dB of maximum gain at 60 GHz operating frequency at very low noise figure of 2.8 dB, which translates to a figure of merit of 16.1 GHz and IIP3 as -14.38 dBm.
Electrical Engineering (MS)
Department, Program, or Center
Electrical Engineering (KGCOE)
Shinde, Tanmay Vinay, "Design, Fault Modeling and Testing Of a Fully Integrated Low Noise Amplifier (LNA) in 45 nm CMOS Technology for Inter and Intra-Chip Wireless Interconnects" (2018). Thesis. Rochester Institute of Technology. Accessed from
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