Abstract

The progression of technology has required smaller devices to achieve faster circuits and more power-efficient systems. However, with supply voltage and device intrinsic gain decreasing, device biasing in deep sub-micron technologies can be challenging. A low-voltage current source is analyzed in a 28 nm CMOS, 0.85 V supply, technology to take into account undesirable effects introduced by aggressively scaled technologies. The analysis includes intrinsic gain degradation as well as short-channel effects to create a more accurate design methodology. Amplifier design challenges in deep sub-micron technologies are discussed along with a DAC bias correction technique. Frequency dependence of output resistance for a simple and a proposed current source is presented. For the proposed current source the frequency dependence of output resistance was found to be dictated by the frequency response of the amplifier. To demonstrate the relevance of current source resistance bandwidth a common-mode logic circuit is considered, and fabrication plans are discussed along with future work.

Library of Congress Subject Headings

Low voltage integrated circuits--Design and construction; Metal oxide semiconductors, Complementary--Design and construction

Publication Date

5-12-2015

Document Type

Thesis

Student Type

Graduate

Degree Name

Electrical Engineering (MS)

Department, Program, or Center

Electrical Engineering (KGCOE)

Advisor

P. R. Mukund

Advisor/Committee Member

James Moon

Advisor/Committee Member

Jing Zhang

Comments

Physical copy available from RIT's Wallace Library at TK7874.66 .Z46 2015

Campus

RIT – Main Campus

Plan Codes

EEEE-MS

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