Power consumption is becoming an increasingly important component of processor design. As technology shrinks both static and dynamic power become more relevant. This is particularly important for the cache hierarchy. The cache portion of a microprocessor contains a large percentage of the total number of transistors in the microprocessor. Therefore the cache consumes a large percentage of both static and dynamic power. When improving power consumption in the past, there has always been a large trade-off between energy savings and performance.
Techniques that reduce power consumption typically have a negative impact on performance. Likewise, when performance is improved it is at the cost of higher energy consumption. Also many current implementations only reduce one kind of power in the cache, either static or dynamic. For a more robust approach that will remain relevant as technology continues to shrink, both aspects of power need to be addressed.
This thesis implements a phase adaptive cache that will reduce both static and dynamic power while having very little impact on the performance. This cache stores the most recently used blocks in one partition that is quick and easy to access. The second partition is placed in drowsy mode to reduce leakage power consumption. In this work, this approach is implemented for all three levels of cache in a multicore architecture. The design is also tested with multithreaded simulations.
The results are measured using an architecture simulator. Simulations of the modified cache structure are compared to those of a baseline unchanged cache hierarchy running on the same machine. These results are compared for both energy savings including static and dynamic power, along with the overall impact on performance. The results in this work show that this cache design produces both dynamic energy and leakage energy savings with a low performance impact.
Library of Congress Subject Headings
Simultaneous multithreading processors--Energy consumption; Computer systems--Energy conservation; Cache memory; Computer architecture--Computer simulation
Computer Engineering (MS)
Department, Program, or Center
Computer Engineering (KGCOE)
Sonia Lopez Alarcon
Kenyon, Samantha Rose, "Drowsy Cache Partitioning for Multithreaded Systems and High Level Caches" (2014). Thesis. Rochester Institute of Technology. Accessed from
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