Abstract

This thesis contains the analysis, design, and implementation of a writable programmable logic array integrated circuit. The WPLA is able to be reprogrammed any number of times as needed. A content addressable scheme is proposed to conduct READ, WRITE, and SEARCH operations in the WPLA. The WPLA is programmed by writing binary data into storage cells associated with each node in the AND/OR planes of the array; the binary data then form the personalities of the PLA. The layout of the WPLA will be implemented using Mentor Graphic's CHIPGRAPH layout editor with 2 µm NMOS technology and MOSIS design rules. The event-driven logic level simulator QUICKSIM, and a MOS circuit level simulator MSIMON, are used to verify the functional and timing behavior of the WPLA.

Library of Congress Subject Headings

Integrated circuits--Design and construction; Programmable array logic

Publication Date

1-1-1988

Document Type

Thesis

Student Type

Graduate

Degree Name

Computer Science (MS)

Department, Program, or Center

Computer Science (GCCIS)

Advisor

James Heliotis

Advisor/Committee Member

Roy S. Czernikowski

Advisor/Committee Member

George A. Brown

Comments

Physical copy available from RIT's Wallace Library at TK7874 .H887 1988

Campus

RIT – Main Campus

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