Kevin Johnson

Abstract

The purpose of this thesis is to show some of the advantages for the asynchronous implementation of a major synchronous structure. Three people were involved with the design of an asynchronous microprocessor modeled after the MIPS R3000 microprocessor. This microprocessor implemented all of the MIPS reduced instruction set, while eliminating the need for synchronous clocking throughout the chip. Paul Fanelli modeled the asynchronous processor using VHDL (hardware description language). Kevin Johnson created circuit level designs and layouts of the arithmetic logic unit and supporting hardware. Scott Siers created circuit level designs and layouts of the instruction fetch, write back, memory and instruction decode stages.

Library of Congress Subject Headings

MIPS R3000 series microprocessors--Design and construction; Microprocessors--Design and construction; Computer architecture; Computer engineering

Publication Date

1-1994

Document Type

Thesis

Student Type

Graduate

Degree Name

Computer Engineering (MS)

Department, Program, or Center

Computer Engineering (KGCOE)

Advisor

George A. Brown, Professor

Advisor/Committee Member

Roy S. Czemikowski

Advisor/Committee Member

Tony H. Chang

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: QA76.8.M522J64 1994

Campus

RIT – Main Campus

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