Reed-Solomon error correcting codes (RS codes) are widely used in communication and data storage systems to recover data from possible errors that occur during data transfer. A growing application of RS codes is Forward Error Correction (FEC) in the Optical Network (OTN G.709), which uses RS(255,239) to support the OTU-3 (43.018 Gbps) standard. There have been considerable efforts in the area of RS architecture for ASIC implementation. However, there appears to be little reported work on efficient RS codec (encoder and decoder) for Field Programmable Gate Arrays (FPGAs), which has increasing interests in industry.
This thesis investigates the implementation and design methodology of the RS(255,239) codec on FPGAs. A portable VHDL code is developed and synthesized for Xilinx's Virtex4 and Altera's StratixII. The FPGA architectures are analyzed and the required design methodologies are adopted to efficiently utilize the available resources. Unfortunately, due to the fixed size of FPGA devices, the RS decoder is not only constrained by the required timing of the system, but also by the size of the targeted device. This research will facilitate the decision-making process for selecting a reconfigurable device for a RS decoder, implementing the Berlekamp-Massey Algorithm.
Library of Congress Subject Headings
Error-correcting codes (Information theory); Field programmable gate arrays--Design and construction; Reed-Solomon codes; Decoders (Electronics); VHDL (Computer hardware description language)
Computer Engineering (MS)
Department, Program, or Center
Computer Engineering (KGCOE)
Shanchieh Jay Yang
Wai, Kenny Chung Chung, "FPGA implementation of Reed Solomon codec for 40Gbps Forward Error Correction in optical networks" (2006). Thesis. Rochester Institute of Technology. Accessed from
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