Abstract

Reed-Solomon error correcting codes (RS codes) are widely used in communication and data storage systems to recover data from possible errors that occur during data transfer. A growing application of RS codes is Forward Error Correction (FEC) in the Optical Network (OTN G.709), which uses RS(255,239) to support the OTU-3 (43.018 Gbps) standard. There have been considerable efforts in the area of RS architecture for ASIC implementation. However, there appears to be little reported work on efficient RS codec (encoder and decoder) for Field Programmable Gate Arrays (FPGAs), which has increasing interests in industry.

This thesis investigates the implementation and design methodology of the RS(255,239) codec on FPGAs. A portable VHDL code is developed and synthesized for Xilinx's Virtex4 and Altera's StratixII. The FPGA architectures are analyzed and the required design methodologies are adopted to efficiently utilize the available resources. Unfortunately, due to the fixed size of FPGA devices, the RS decoder is not only constrained by the required timing of the system, but also by the size of the targeted device. This research will facilitate the decision-making process for selecting a reconfigurable device for a RS decoder, implementing the Berlekamp-Massey Algorithm.

Library of Congress Subject Headings

Error-correcting codes (Information theory); Field programmable gate arrays--Design and construction; Reed-Solomon codes; Decoders (Electronics); VHDL (Computer hardware description language)

Publication Date

2-2006

Document Type

Thesis

Student Type

Graduate

Degree Name

Computer Engineering (MS)

Department, Program, or Center

Computer Engineering (KGCOE)

Advisor

Shanchieh Jay Yang

Advisor/Committee Member

Marcin Lukowiak

Advisor/Committee Member

Doug Bush

Comments

Physical copy available from RIT's Wallace Library at TK5102.96 .C58 2006

Campus

RIT – Main Campus

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