Cryptographic algorithms such as the Advanced Encryption Standard (AES) are vulnerable to side channel attacks. AES was once thought to be impervious to attacks, but this proved to be true only for a mathematical model of AES, not a physical realization. Hard- ware implementations leak side channel information such as power dissipation. One of the practical SCA attacks is the Differential power analysis (DPA) attack, which statistically analyzes power measurements to ﬁnd data-dependent correlations.
Several countermeasures against DPA have been proposed at the circuit and logic level in conventional technologies. These techniques generally include masking the data inside the algorithm or hiding the power proﬁle. Next generation processors bring in additional challenges to mitigate DPA attacks, by way of heterogeneity of the devices used in the hardware realizations. Neuromemristive systems hold potential in this domain and also bring new challenges to the hardware security of cryptosystems.
In this exploratory work, a neuromemristive architecture was designed to compute an AES transformation and mitigate DPA attacks. The random power proﬁle of the neuromemristive architecture reduces the correlations between data and power consumption. Hardware primitives, such as neuron and synapse circuits were developed along with a framework to generate neural networks in hardware.
An attack framework was developed to run DPA attacks using different leakage models. A baseline AES cryptoprocessor using only CMOS technology was attacked successfully.
The SubBytes transformation was replaced by a neuromemristive architecture, and the proposed designs were more resilient against DPA attacks at the cost of increased power consumption.
Library of Congress Subject Headings
Cyberterrorism--Prevention; Memristors; Data encryption (Computer science)
Computer Engineering (MS)
Department, Program, or Center
Computer Engineering (KGCOE)
Donahue, Colin R., "Mitigating Differential Power Analysis Attacks on AES using NeuroMemristive Hardware" (2014). Thesis. Rochester Institute of Technology. Accessed from
RIT – Main Campus
Physical copy available from RIT's Wallace Library at QA76.9.A25 D66 2014