Abstract

Charge-injection devices (CID's) have been around almost as long as charge-coupled devices (CCD's), yet have generally been overlooked for solid state imaging applications due to their slower operating speeds. However, CID arrays offer advantages over CCD based arrays for certain applications where spectral response and/or X-Y addressing are required. In order to fabricate CID based imaging arrays, a single level poly CMOS (p-well) process has been modified into a double level poly CMOS (p-well) process that will allow fabrication of both imaging structures and drive circuitry. These modifications are optimized for CID based structures, yet will also allow working CCD based arrays to be fabricated with this process. Measurements obtained from processed wafers were compared to values obtained using SUPREM IV simulation software from Technology Modeling Associates Inc. and after analysis, further recommendations were made to improve the process.

Library of Congress Subject Headings

Semiconductors--Design and construction; Integrated circuits--Design and construction; Imaging systems--Design and construction

Publication Date

1996

Document Type

Thesis

Department, Program, or Center

Microelectronic Engineering (KGCOE)

Advisor

Fuller, Lynn

Advisor/Committee Member

Hirschman, Karl

Advisor/Committee Member

Labberts, Gerrit

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7871.85 .S356 1996

Campus

RIT – Main Campus

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