Abstract

A study on the influence of phosphorus implanted source/drain features on the off-state performance of transistors fabricated in thin-film crystalline silicon at low temperature is presented. Complementary Metal Oxide Semiconductor (CMOS) thin film transistors (TFTs) were fabricated on silicon-on-insulator (SOI) substrates; both NFET and PFET devices in the same p-type layer. Lightly Doped Drain (LDD) features were implemented on NFETs, and a surface-halo source barrier (N-barrier) was implemented on PFETs, using a common implant step. A new mask set was designed with fine resolution of gate offset to investigate small changes in placement of the LDD/ N-barrier structures. The focus of this investigation was the off-state characteristics of the devices; the implanted features were designed to help suppress the effects of Gate Induced Drain Leakage (GIDL) and Drain Induced Barrier Lowering (DIBL). Along with the mask design offsets, a number of process variations resulted in TFTs with different degrees of gate overlap and device symmetry. Electrical device characteristics are presented in the study, with comparisons to devices simulated using Silvaco ® Atlas.

Library of Congress Subject Headings

Silicon-on-insulator technologyThin film transistors--Design and construction; Thin film transistors--Noise; Metal oxide semiconductors, Complementary--Design and construction; Integrated circuits--Masks

Publication Date

2009

Document Type

Thesis

Department, Program, or Center

Microelectronic Engineering (KGCOE)

Advisor

Hirschman, Karl D.

Advisor/Committee Member

Moon, James

Advisor/Committee Member

Rommel, Sean

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7871.96.T45 S46 2009

Campus

RIT – Main Campus

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