The integration of Si-based resonant interband tunnel diodes with CMOS
Physical copy available from RIT's Wallace Library at TK7871.99.M44 S73 2003
The first demonstration of the integration of CMOS and Si/SiGe resonant interband tunnel diode (RITD) is reported in this study. RTD-FET circuits in III-V materials have demonstrated improved speed and power capability in electronic circuits. In Si-based material, recent breakthrough in Si/SiGe RITD grown using molecular beam epitaxy (MBE) made the integration with CMOS possible. Discrete Si/SiGe RITDs typically exhibit a PVCR of 3.6 and Jp of 0.3 kA/cm2. The CMOS devices used in this study features (1) double-well technology, (2) localized oxidation on silicon (LOCOS) to provide isolation between devices, (3) SiO2 gate dielectric of 370 Å thick, (4) highly n-doped polysilicon gate, (5) self-aligned source and drain formation, and (6) Al doped with Si for contact and metallization. Based on thermal budget considerations, the strategy employed was to integrate the RITD after all CMOS high thermal front-end steps, up to the source/drain formation, but prior to metallization. The tunnel diodes were grown through openings in a 300 nm-thick chemical vapor deposition (CVD) oxide. The RITDs were also grown a top of p+ implanted regions of the source and drain of the PMOS. Process integration challenges studied in this work include the effect of pre-growth substrate cleaning, patterned growth and overgrowth methods, and residual implant damage. Si/SiGe RITDs grown by MBE have been monolithically integrated with CMOS for the first time. The integrated devices resulted in a PVCR of 2.8 and Jp of 0.3 kA/cm2 at room temperature, which enables the realization of RITD/CMOS circuitry. For the first time, a NMOS-RITD MOBILE latch was demonstrated in Si. This logic element enables digital and ternary circuit design for high density storage.