A modular 2-micron BiCMOS process was developed from an existing 2-micron N-Well CMOS process. The process maintains compatibility with the existing 2- micron CMOS design rules and design library, meets the NPN device parameter targets supplied, and utilizes present manufacturing operations and equipment, with a minimum number of additional masks and steps. NPN transistor parameter targets were determined from intended technology applications. Process integration options are introduced and evaluated. A procedure for process latitude determination and process optimization is presented.
Library of Congress Subject Headings
Metal oxide semiconductors, Complementary; Bipolar integrated circuits
Department, Program, or Center
Electrical Engineering (KGCOE)
Guidash, R. Michael, "Development of a modular 2-micron BiCMOS process from an existing 2-micron n-well CMOS process" (1991). Thesis. Rochester Institute of Technology. Accessed from
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