The design of a microprocessor based hybrid system for digital error correction is presented. It is shown that such a system allows for implementation of several cyclic codes at a variety of throughput rates providing variable degrees of error correction depending on current user requirements. The theoretical basis for encoding and decoding of binary BCH codes is reviewed. Design and implementation of system hardware and software are described. A method for injection of independent bit errors with controllable statistics into the system is developed, and its accuracy verified by computer simulation. This method of controllable error injection is used to test performance of the designed system. In analysis, these results demonstrate the flexibility of operation provided by the hybrid nature of the system. Finally, potential applications and modifications are presented to reinforce the wide applicability of the system described in this thesis.
Library of Congress Subject Headings
System design; Error-correcting codes (Information theory)
Department, Program, or Center
Electrical Engineering (KGCOE)
Sohn, Peter H., "A Microprocessor based hybrid system for digital error correction" (1984). Thesis. Rochester Institute of Technology. Accessed from
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