The predominant integrated circuit fabrication technologies used for VLSI devices are CMOS, and BiCMOS. The goal of this work was to develop a CMOS process that could be converted into a BiCMOS technology. For this reason an N-Well CMOS process was selected, and fabricated in the Microelectronic Engineering clean room. This paper reviews the test chip design, process simulation, fabrication, and electrical characterization of this process. The device fabrication was successful, and the electrical testing clearly indicated what measures need to be taken to improve the process.
Library of Congress Subject Headings
Metal oxide semiconductors, Complementary
Department, Program, or Center
Electrical Engineering (KGCOE)
Price, David T., "N-Well CMOS process integration" (1992). Thesis. Rochester Institute of Technology. Accessed from
RIT – Main Campus