The purpose of this thesis is to demonstrate one method of statistical parameter extraction and show some of the advantages of statistical models. The method of extraction discussed, parameter domain statistics, is ideal for use in the classroom, due to its simplicity and ease of implementation. Another advantage is the minimal statistical knowledge required to understand this process. The test chip design was a modification of the test chip designed by Bert Berends. An N-Well CMOS lot was processed and models extracted using IC-CAP From these models, parameter domain statistics were performed - the model parameters were used to create an average and 3a models. Additionally, the process was simulated with TSUPREM 4 and models were extracted from simulation and compared to the average models measured from silicon. Through use of a threshold adjustment implant split, wafers were fabricated with symmetrical NMOS and PMOS threshold voltages. The threshold voltages followed the trends predicted by simulation, and mobility was determined to be independent of threshold adjustment implant dose. Lastly, the buried channel, PMOS device parameters exhibited a larger variation than the NMOS parameters.
Library of Congress Subject Headings
Metal oxide semiconductors, Complementary--Design and construction--Data processing; Integrated circuits--Design and construction--Data processing; Metal oxide semiconductors, Complementary--Design and construction--Mathematical models; Integrated circuit
Department, Program, or Center
Computer Engineering (KGCOE)
Hildreth, Scott, "Statistical SPICE parameter extraction for an n-well CMOS process" (1995). Thesis. Rochester Institute of Technology. Accessed from
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