The tunneling-FET (TFET) has been identified as a prospective MOSFET replacement technology with the potential to extend geometric and electrostatic scaling of digital integrated circuits. However, experimental demonstrations of the TFET have yet to reliably achieve drive currents necessary to power large scale integrated circuits. Consequentially, much effort has gone into optimizing the band-to-band tunneling (BTBT) efficiency of the TFET. In this work, the Esaki tunnel diode (ETD) is used as a short loop element to map and optimize BTBT performance for a large design space. The experimental results and tools developed for this work may be used to (1) map additional and more complicated ETD structures, (2) guide development of improved TFET structures and BTBT devices, (3) design ETDs targeted BTBT characteristics, and (4) calibrate BTBT models. The first objective was to verify the quality of monolithically integrated III-V based ETDs on Si substrates (the industry standard). Five separate GaAs/InGaAs ETDs were fabricated on GaAs-virtual substrates via aspect ratio trapping, along with two companion ETDs grown on Si and GaAs bulk substrates. The quality of the virtual substrates and BTBT were verified with (i) very large peak-valley current ratios (up to 56), (ii) temperature measurements, and (iii) deep sub-micron scaling. The second objective mapped the BTBT characteristics of the In1-xGaxAs ternary system by (1) standardizing the ETD structure, (2) limiting experimental work to unstrained (i) GaAs, (ii) In0.53Ga0.47As, and (iii) InAs homojunctions, and (3) systematically varying doping concentrations. Characteristic BTBT trendlines were determined for each material system, ranging from ultra-low to ultra-high peak current densities (JP) of 11 μA/cm2 to 975 kA/cm2 for GaAs and In0.53Ga0.47As, respectively. Furthermore, the BTBT mapping results establishes that BTBT current densities can only be improved by ~2-3 times the current record, by increasing doping concentration and In content up to ~75%. The E. O. Kane BTBT model has been shown to accurately predict the tunneling characteristics for the entire design space. Furthermore, it was used to help guide the development of a new universal BTBT model, which is a closed form exponential using 2 fitting parameters, material constants, and doping concentrations. With it, JP can quickly be predicted over the entire design space of this work.
Microsystems Engineering (Ph.D.)
Department, Program, or Center
Microsystems Engineering (KGCOE)
Sean L. Rommel
Santosh K. Kurinec
Pawlik, David John, "Comprehensive Mapping and Benchmarking of Esaki Diode Performance" (2013). Thesis. Rochester Institute of Technology. Accessed from
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