Abstract

One way to increase the performance of a processing unit is to exploit implicit parallelism. Exploiting this parallelism requires a processor to dynamically select instructions in a serial instruction stream which can be executed in parallel. As operations are computed concurrently, an execution speedup will occur. This thesis studies how effectively implicit parallelism could be exploited in the Scalable Pro cessor Architecture (SPARC)[9], a reduced instruction set architecture developed by Sun Microsystems. First an analysis of SPARC instruction traces will determine the optimal speedup that would be realized by a processor with infinite resources. Next, an analytical model of a parallelizing processor will be developed and used to predict the effects of limited resources on optimal speedup. Lastly, a SPARC simulator will be employed to determine the actual speedup of resource limited configurations, and the results will be correlated with the analytical model.

Library of Congress Subject Headings

Computer architecture; Parallel processing (Electronic computers)

Publication Date

1990

Document Type

Thesis

Department, Program, or Center

Computer Science (GCCIS)

Advisor

Heliotis, James

Advisor/Committee Member

Miemi, Rayno

Advisor/Committee Member

Lutz, Michael

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: QA76.9.A73 A86 1990

Campus

RIT – Main Campus

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