Brian Hughes

Abstract

Multimedia computer architecture extensions for Hennessy and Patterson's DLX architecture are developed following the study of multimedia applications and existing multimedia architecture extensions. Support for the extensions is added to a VHDL superscalar DLX CPU model as well as a DLX assembler. Key functions used in digital video encoding and decoding are modified to use the extensions, and simulations are undertaken using the VHDL model to determine the speedup offered by the extensions for these functions. The results of the simulations are used to calculate the application speedup based on the function speedup and the fraction of the time that each application spends executing each function. It is shown that the superscalar CPU design limits the performance gain offered by the extensions, and concluded that the effectiveness of the extensions is further limited by the fraction of the application code that can make use of them.

Library of Congress Subject Headings

Multimedia systems--Software--Testing; RISC microprocessors; Software engineering; Computer architecture

Publication Date

6-1-1997

Document Type

Thesis

Department, Program, or Center

Computer Engineering (KGCOE)

Advisor

Chang, Tony

Advisor/Committee Member

Shaaban, Muhammad

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: QA76.575 .H844 1997

Campus

RIT – Main Campus

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