Multimedia computer architecture extensions for Hennessy and Patterson's DLX architecture are developed following the study of multimedia applications and existing multimedia architecture extensions. Support for the extensions is added to a VHDL superscalar DLX CPU model as well as a DLX assembler. Key functions used in digital video encoding and decoding are modified to use the extensions, and simulations are undertaken using the VHDL model to determine the speedup offered by the extensions for these functions. The results of the simulations are used to calculate the application speedup based on the function speedup and the fraction of the time that each application spends executing each function. It is shown that the superscalar CPU design limits the performance gain offered by the extensions, and concluded that the effectiveness of the extensions is further limited by the fraction of the application code that can make use of them.
Library of Congress Subject Headings
Multimedia systems--Software--Testing; RISC microprocessors; Software engineering; Computer architecture
Department, Program, or Center
Computer Engineering (KGCOE)
Hughes, Brian, "Design and evaluation of multimedia extensions for the DLX architecture" (1997). Thesis. Rochester Institute of Technology. Accessed from
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