Abstract

An extensible, scalable stack-based microprocessor architecture is developed and discussed. Several unique features of the architecture, including its non-memory oriented interface, and its use of a stack for holding and executing code, are detailed. A programmed model is used to verify the architecture, and a hardware implementation of a small-scale version of the architecture is constructed and tested. Notes for future implementations are provides. Possible applications based on the latest technological trends are discussed, and topics for further research into the architecture are listed.

Library of Congress Subject Headings

Computer architecture; Microprocessors--Design and construction; Computer engineering

Publication Date

11-1-1993

Document Type

Thesis

Department, Program, or Center

Computer Engineering (KGCOE)

Advisor

Chang, Tony

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: QA76.9.A73D558 1993

Campus

RIT – Main Campus

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