An advanced process for fabrication of 0.25 μm CMOS transistors has been demonstrated. This process is designed for transistors with Lpoly = 0.25 μm and Leffective = 0.2 um on 150 mm (6”) silicon wafers. Devices with Leffective of 0.2 um and smaller have been tested and found operational. A 0.25 um NMOS transistor with drain current of 177 μA/μm at VG=VD=2.5 V and a PMOS transistor with drain current of 131 μA/μm at VG=VD=-2.5 V are reported. The threshold voltages are 1.0 V for the NMOS and -0.735 V for the PMOS transistors. These 0.25 um NMOS and PMOS are the smallest transistors ever fabricated at RIT. Many processes have been integrated to produce the final CMOS devices, including: 50 Å gate oxide with N2O, shallow trench isolation by chemical mechanical planarization (CMP), dual doped polysilicon gates for surface channel devices, ultra-shallow low doped source/drain extensions using low energy As and BF2 ions, rapid thermal dopant activation, Si3N4 sidewall spacers, TiSi2 salicide source/drain contacts and gates, uniformly doped twin wells, contact cut RIE and 2 level aluminum metallization.
Library of Congress Subject Headings
Metal oxide semiconductors, Complementary--Design and construction; Transistors--Design and construction; Microelectronics--Design and construction
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Department, Program, or Center
Microelectronic Engineering (KGCOE)
Aquilino, Michael, "Development of deep submicron CMOS process for fabrication of high performance 0.25 nm transistors" (2006). Thesis. Rochester Institute of Technology. Accessed from
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