Abstract
A timing simulator, called TIMSIM, has been developed which performs gate level simulation of simple digital logic circuits. TIMSIM has a library of twelve standard TTL gate elements and memory elements. These elements incorporate various features including single outputs, multiple outputs, non-symmetric inputs, and memory states. TIMSIM uses a rise-fall delay model and three values to represent a signal's logic level.
Library of Congress Subject Headings
Logic circuits--Design--Simulation methods; Computer simulation; Computer-aided design
Publication Date
1988
Document Type
Thesis
Department, Program, or Center
Computer Science (GCCIS)
Advisor
Brown, George
Advisor/Committee Member
Miemi, Rayno
Advisor/Committee Member
Anderson, Peter
Recommended Citation
Heintz, Kathryn D., "A timing simulator" (1988). Thesis. Rochester Institute of Technology. Accessed from
https://repository.rit.edu/theses/152
Campus
RIT – Main Campus
COinS
Comments
Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7888.4 .H443 1988