A timing simulator, called TIMSIM, has been developed which performs gate level simulation of simple digital logic circuits. TIMSIM has a library of twelve standard TTL gate elements and memory elements. These elements incorporate various features including single outputs, multiple outputs, non-symmetric inputs, and memory states. TIMSIM uses a rise-fall delay model and three values to represent a signal's logic level.
Library of Congress Subject Headings
Logic circuits--Design--Simulation methods; Computer simulation; Computer-aided design
Department, Program, or Center
Computer Science (GCCIS)
Heintz, Kathryn D., "A timing simulator" (1988). Thesis. Rochester Institute of Technology. Accessed from
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