The design and simulation of RIT's sub-micron CMOS process is studied in this work. The work has demonstrated a process capable of producing working transistors with a channel length of 0.5um. New advancements such as dual well, low doped drain (LDD) regions and self-aligned silicides are a few mentioned highlights. The devices will be fabricated on 6" wafers using equipment recently donated to the RIT Microelectronic Engineering cleanroom facility. This calls for characterization of the new processes and equipment for optimized results. Device simulation was performed using MicroTec 2D Process/Device simulator from Siborg Systems. Simulated threshold voltage for the NFET device was on target, whereas the PFET transistors will require further process improvement.
Library of Congress Subject Headings
Metal oxide semiconductors, Complementary--Design and construction; Metal oxide semiconductors, Complementary--Simulation methods; Digital integrated circuits--Design and construction
Department, Program, or Center
Microelectronic Engineering (KGCOE)
Bhaskaran, Suraj, "Design of RIT's sub-micron CMOS process" (2000). Thesis. Rochester Institute of Technology. Accessed from
RIT – Main Campus
Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7871.99.M44 B5 2000