Abstract
Increased design complexity has resulted in the need for efficient verification. The verification process is crucial for discovering and fixing bugs prior to fabrication and system integration. However, as designs increase in complexity, the use of traditional verification techniques with VHDL and Verilog may fall short to provide a proper toolset. Especially when performing verification on designs involving audio signal processing, untested corner cases and bugs may result in significant and sometimes undiscovered processing errors. This paper explores the use of SystemVerilog and the universal verification methodology (UVM) class library to verify a pipelined floating-point multiplier (FMULT) within the adaptive differential pulse code modulation (ADPCM) specification.
Publication Date
12-2019
Document Type
Master's Project
Student Type
Graduate
Degree Name
Electrical Engineering (MS)
Department, Program, or Center
Electrical Engineering (KGCOE)
Advisor
Mark A. Indovina
Advisor/Committee Member
Sohail A. Dianat
Recommended Citation
Marsaw, Nicholas J., "UVM Verification of a Floating Point Multiplier" (2019). Thesis. Rochester Institute of Technology. Accessed from
https://repository.rit.edu/theses/10327
Campus
RIT – Main Campus
