The continuous demand for ultra-high resolution and improved video performance on increasingly larger active-matrix displays has advanced the research field of thin film transistors (TFTs) materials, processes and devices. Performance improvements demonstrated by amorphous Indium-Gallium-Zinc-Oxide (IGZO) TSTs has enabled a commercialized backplane technology adopted for AM-OLED displays, providing advantage in device performance and uniformity at a much lower cost than Low Temperature Poly-crystalline Silicon (LTPS). However as the display size gets larger and the pixel density increases, charge transfer from the column driver to the pixel through the addressed row TFT within the required time interval becomes increasingly difficult. As the pixel size shrinks and the panel size grows, interconnects that must be scaled down in cross-section have to transport charge over longer distances.In addition, as the numbers of rows increase in a display, the time allowed for charge transfer decreases to maintain a high image refresh frequency. These challenges must be addressed by lower interconnect delay, thus the advantages in transitioning to Cu for long interconnect rows and columns. The gate electrodes are usually implemented as an appendage of the row interconnect, thus Cu-gate TFTS would avoid added process complexity while supporting high-speed interconnects and low production costs. The following work presents a study on Cu-gate integration and potential channel contamination on bottom-gate IGZO TSTs with a newly established baseline process. Cu was used in place to Mo as the gate electrode, with an underlying Ti layer to promote adhesion to the oxidized silicon substrate. The experimental design input factors included the option of a Ti capping layer on the Cu-gate, and the anneal conditions of the gate dielectric (PECVD SiO2) prior to IGZO sputtering. Distinct differences in physical and electrical responses over all treatment combinations were identified. Experimental results demonstrated that while the Ti capping layer promoted adhesion to the gate dielectric, it served as a source of contamination on pre-annealed treatments causing pronounced electrical characteristic shifting and dielectric failure. The anneal process was found to promote adhesion between the Cu-gate and the gate oxide without the use of Ti capping layer, as well as reduce oxide charge levels. Copper contamination did not appear to be an issue in treatment conditions at or below 400C, however pitting of the gate electrode occurred at anneal temperature above 400C, as well as electrical results that suggest evidence of Cu contamination. Visual observations and electrical characteristics are presented wit ha detailed discussion on comparisons between treatment combinations, with reference to the baseline IGZO devices.
Microelectronic Engineering (MS)
Department, Program, or Center
Microelectronic Engineering (KGCOE)
Sethupathi, Harithshanmaa, "A Study on Copper-Gate Integration with Titanium Interface Layers for IGZO TFTs" (2019). Thesis. Rochester Institute of Technology. Accessed from
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