Engineering Source/Channel/Drain Regions for PMOS TFTs in Flash Lamp Annealed Polycrystalline Silicon
The flat panel industry requires high performance semiconductor materials to withstand the growth rate in the standards of display quality due to the inability of amorphous silicon (a-Si) to support the next generation display manufacturing. Upon research of other materials, low temperature polycrystalline silicon (LTPS) has exhibited the maximum potential considering its high charge carrier mobility. Currently, industry has been employing excimer laser annealing (ELA) process for production of polycrystalline silicon from amorphous silicon which is an expensive process and limits its usability to small screen displays. Flash lamp annealing (FLA) is another approach that is cost efficient and can be utilized for large glass panels and presents itself as a potential candidate to replace ELA; however challenges in obtaining uniform morphology over large areas must be addressed.
Previous work on FLA polycrystalline silicon TFTs demonstrated high carrier mobility but exhibited scalability issues due to liquid-phase dopant diffusion. To avoid this issue, dopants were ion implanted post-FLA, then activated through furnace annealing at relatively low temperatures (T ≤ 700 °C). This procedure resulted in reasonable dopant activation, and p-channel TFT operating characteristics with an effective hole channel mobility of 40 – 50 cm2/(Vs). However 700 °C annealing was required to promote TFT electrical performance, which is beyond a practical limit for large panel manufacturing. This work presents on strategies which use FLA for both crystallization and dopant activation processes.
An initial study explored low intensity FLA for partial solid-phase crystallization of a-Si to realize microcrystalline material with mixed-phase morphology, with crystallization and dopant activation processes occurring simultaneously. Exceedingly high series resistance rendered the material incapable of demonstrating working TFTs. Efforts were then redirected based on the success of an approach using pre-amorphization of FLA LTPS by Si+ ion implantation, followed by boron ion implantation and activation through solid-phase crystallization in the source/drain regions. The pre-amorphization process demonstrated improved TFT characteristics on both furnace anneal treatments done at lower temperature (T = 630 °C) and FLA activation treatments. This approach was modified to include a furnace anneal treatment in between the Si+ pre-amorphization and boron ion implant processes, which following FLA activation has yielded the lowest sheet resistance obtained thus far (Rs < 400 Ω/□). This high level of boron activation suggests the lack of extended defects, and thus the potential to realize an improvement in transitions at the source/channel and channel/drain interface regions.
Library of Congress Subject Headings
Flat panel displays--Materials; Metal oxide semiconductors--Design and construction; Tunnel field-effect transistors; Polycrystalline semiconductors; Annealing of crystals
Microelectronic Engineering (MS)
Department, Program, or Center
Microelectronic Engineering (KGCOE)
Karl D. Hirschman
Garg, Viraj, "Engineering Source/Channel/Drain Regions for PMOS TFTs in Flash Lamp Annealed Polycrystalline Silicon" (2019). Thesis. Rochester Institute of Technology. Accessed from
RIT – Main Campus