Publication Date
1999
Document Type
Paper
Abstract
An alternative to the single floating gate on a standard EEPROM device could be a continuous semi insulating layer in which the distribution of charge can be controlled. By partial oxidation of porous silicon, a new material named Oxide Passivated Nanocrystalline Silicon (OPNSi) is formed, which has embedded Si nanocrystals in a porous glass structure. With oxide barriers between silicon nanocrystals, carriers can be confined to the silicon crystallites or trapped at interface states on the surface of these nanocrystals. With the assistance of an electric field, carriers can undergo direct tunneling through the very thin barriers and alter the charge distribution within the OPNSi layer. The placement of charge within the layer will determine the field-effect on the underlying silicon substrate. A nondestructive read would take place at low control-gate bias, and possibly result in faster write/erase cycles compared to traditional EEPROM. Another fundamental limitation of today’s flash EEPROM is that each memory cell requires a pass-gate and a 3-terminal transistor structure, which limits the size of each cell. The OPNSi Diode will also be investigated as a possible candidate for a 2-terminal X point array memory device.
Recommended Citation
Gurcan, Burcay
(1999)
"Oxide Passivated Nanocrystalline Silicon Trap-Controlled memory Devices,"
Journal of the Microelectronic Engineering Conference: Vol. 9:
Iss.
1, Article 7.
Available at:
https://repository.rit.edu/ritamec/vol9/iss1/7