SUPREM4 simulation for lateral DMOSFET’s are discussed, as well as the Medici simulation of their electrical characteristics. The actual processing parameters of the device simulation are shown, and the theory surrounding device operation is discussed. The three electrical tests — IDNDS characteristic, VT determination, and the breakdown VDS are explained with the testing method used for each. The four process variations — substrate doping, well dose, well drive in temperature, and oxidation temperature are presented as well as their theoretical effects on device performance. Finally, the results of the electrical tests are presented with conclusions regarding the effects of the mentioned process alterations on device performance.
"Simulation and Tolerance Determination for Lateral CMOS Devices,"
Journal of the Microelectronic Engineering Conference: Vol. 8
, Article 5.
Available at: https://scholarworks.rit.edu/ritamec/vol8/iss1/5