Unlike conventional hard programmed gate arrays, the Field Programmable Logic Array (FLPA) offers the end user the ability to instantly change the outputted function of the circuit through an external electronic programming sequence. This project outlines the design and fabrication of a P Well CMOS NOR logic FPLA. Consisting of roughly 1,400 transistors, three major functional components were designed: Floating Tunnel Oxide EEPROM memory bank, an EEPROM addressing system, and a 3 input I 3 output / 2 return state programmable logic array. Fabrication was carried out at the RIT fabrication facility and upon testing the completed devices it was found that the NMOS devices were too leaky for proper circuit operation. This was due to a partially blocked channel stop implant.
"Design and Fabrication of a Field Programmable Logic Array,"
Journal of the Microelectronic Engineering Conference: Vol. 8
, Article 2.
Available at: https://scholarworks.rit.edu/ritamec/vol8/iss1/2