Low Temperature Oxide (LTO) sidewall spacers have been successfully fabricated using etchback an technique. The process for forming these features was optimised for repeatibility for RIT's sub-micron CMOS. In addition, a reliable process for forming low resistive self aligning titanium silicide was also developed using these sidewall spacers.
Bhaskaran, S K.
"Formation of Sidewall Spacers and Titanium Salicide for RIT's Sub-micron CMOS,"
Journal of the Microelectronic Engineering Conference: Vol. 6
, Article 6.
Available at: https://scholarworks.rit.edu/ritamec/vol6/iss1/6