A 126 bit by one bit NMDS static RAM was designed following design rules for RIT’s standard four layer NMDS process. Verification of working devices was done using the SPICE circuit simulator, but some concerns exist with this because of assumptions made in model parameters. Fabrication was an intended goal of this project, but time restraints allowed only masks to be made.
"Design and Fabrication of Five Microns NMOS SRAM,"
Journal of the Microelectronic Engineering Conference: Vol. 5
, Article 4.
Available at: https://scholarworks.rit.edu/ritamec/vol5/iss1/4