A bilevel metallization process using aluminum with 1~ silicon for the Metal 1 layer, pure aluminum for the Metal 2 layer, and Accuglass X-11 311 Series spin-on glass for the interlevel dielectric was investigated. Problems encountered in via etching with previous bilevel work were eliminated by using a modified buffered HF etchant. Vias down to 6x6um in size were found to conduct and have resistances less than 1 Ohm. Spin-on glass coating processes, however, were still in need of refinement, as numerous pinholes were observed over the aluminum regions.
Bailey, Michael J.
Journal of the Microelectronic Engineering Conference: Vol. 5
, Article 1.
Available at: https://scholarworks.rit.edu/ritamec/vol5/iss1/1