A double level polysilicon self-aligned PMOS process was used to fabricate an integrator circuit using a switch capacitor configuration at the input of an op amp. This process includes a spin-on dopant step to dope the first level of polysilicon while also doping the source and drain of the transistors on the design, thus creating self-aligned gates. The dielectric for the double polysilicon capacitors was a dry oxide on doped polysilicon which also served as the contact cut mask. Electrical testing included several test structures to evaluate process level performance. Problems with doping of the first polysilicon layer did not give good result which caused the circuit not to work. Several resistors did work on the Diffusion and second polysilicon layers.
Plevniak, Sally A.
"Device Fabrication Using a Double Level Polysilicon Self-Aligned PMOS Process,"
Journal of the Microelectronic Engineering Conference: Vol. 4
, Article 28.
Available at: https://scholarworks.rit.edu/ritamec/vol4/iss1/28