Novel test chip structures isolating process problems in certain device regions were designed in area ratios of lx,4x, and 16x in order to investigate sizing trends. The upper three levels of an NMOS process (poly, dielectric, and metal) were fabricated. Metal line integrity structures were tested on a pass or fail basis. Results show that problems did occur in the metal patterning steps causing shorts between adjacent lines. The actual processing steps (photolithography or etching) that were responsible could not be determined without much further testing.
"A Diagnostic Test Chip for NMOS Processing,"
Journal of the Microelectronic Engineering Conference: Vol. 4
, Article 17.
Available at: https://scholarworks.rit.edu/ritamec/vol4/iss1/17