Emitter Coupled Logic (ECL) gates were fabricated on a n-epi layer. SUPREM was used to simulate the fabrication including junction depth and sheet resistance. The Integrated Circuit Editor was used to layout the design based on SUPREM parameters. SPICE was also used to confirm the proper operation of the devices. Testing was limited due to a lack of a probe card for the logic analyzer. But, an npn transistor was tested with a gain of one indicating a working device was present. A subcollector implant was not performed due to the time constrains placed on the project.
Bush, John J.
Journal of the Microelectronic Engineering Conference: Vol. 3
, Article 6.
Available at: https://scholarworks.rit.edu/ritamec/vol3/iss1/6