A set of standard nMOS cells was designed following the MOSIS lambda-based design rules, with a lambda of 2.0 microns. The nMOS process was modeled using SUPREM II, and each of the cells was simulated in SPICE. The cells, an inverter, two, three, and four input NANDs and NORs, NAND and NOR RS flip-flops, a 2-bit Multiplexer, and a 2-bit Demultiplexer/Decoder, were designed with ICE, an in house CAD tool.
"nMOS Standard Cell Library,"
Journal of the Microelectronic Engineering Conference: Vol. 3
, Article 32.
Available at: https://scholarworks.rit.edu/ritamec/vol3/iss1/32