SUPREM simulations were run to determine a junction depth of 3um and a sheet resistance of approximately 5kohms/square to be used in wells for CMOS fabrication. From these results an experiment involving an implant energy of SO KeV, doses of 4E12/cm2, and 8E12/cm2, drive-in temperatures of 1100C and 1150C, and drive-in times between 2 and B hours was performed. Sheet resistances, measured using a four point probe, and junction depth, measured using a groove and stain tool, correlated well to SUPREM simulations.
"Characterization of Wells for the CMOS Process,"
Journal of the Microelectronic Engineering Conference: Vol. 3
, Article 3.
Available at: https://scholarworks.rit.edu/ritamec/vol3/iss1/3