The biristor is a device that has interesting I-V characteristics. When it is current driven the reference device exhibits neural spiking. This neural spiking is characterized by a differing voltage at a steady current. If all of the devices on the chip that was designed exhibit this neural spiking behavior it has the potential of being used as a nueromorphic chip given its layout. The other method of operation is one in which a hysteresis loop is formed. This hysteresis loop can be used for hardware based encryption. This is because the device acts differently to the same stimulus based on previous results. The biristor that was fabricated at RIT was a vertical device modeled after the work of Dr. JinWoo Han and Dr. Meyyapan however it did not appear to have either of these two operating modes and instead appeared to exhibit two stable operating states. The devices that were fabricated at RIT were significantly larger by a factor of roughly 5 in the smallest case than those fabricated by Han and Meyyapan. The sweep from low to high results in higher current while the sweep from high to low results in significantly lower current. This different result leads to the question of whether process variability or device size lead to a difference in I-V characteristics.
"Biristor Array Investigation,"
Journal of the Microelectronic Engineering Conference: Vol. 25
, Article 17.
Available at: https://scholarworks.rit.edu/ritamec/vol25/iss1/17