As process nodes shrink, analog design increasingly becomes difficult due to space, signal, and noise concerns. With highly synthesized digital design, analog design innovation lags as these specific considerations are to be accounted for. The analog to digital converter, proposed by Weaver et al., is a completely digital design relying on comparator offsets to produce a digital counter that tracks the difference between the input voltage and a reference voltage. To soon be fabricated on GlobalFoundry’s 130 nm CMOS process, the proposed 5-bit ADC uses approximately 90,000 transistors with 1,500 comparators and a full-adder tree consisting of 1,500 adders to produce a digital output with a reference voltage of 500 mV and a range of ± 50 mV.
"Stochastic ADC using Standard Cells: Design, Implementation and Eventual Fabrication of a 4.7-bit ADC,"
Journal of the Microelectronic Engineering Conference: Vol. 22
, Article 12.
Available at: https://scholarworks.rit.edu/ritamec/vol22/iss1/12