The aim of this project is to develop a dry etching process that could be utilized to realize high aspect ratio fins. The traditional planar silicon transistor has seen amazing development ever since it became the workhorse of the semi conductor industry and the dominant way of realizing logic and analog circuits. However as its gate channels length is scaled down, the transistor encounters issues termed short channel effects and which has sprouted an extensive research into future replacements for the planar MOSFET. One of such devices is the Fin Field Effect Transistor or FinFET. Most of the FinFET fabrication processes rely heavily on a highly anisotropic etching process to realize very thin fins. This report details the investigation into the possible chemistries used for anisotropic etching, further exploration and improvement of the process on wafers pieces. In the end, the report describes the transfer of the Silicon etch from the wafer pieces to a full six inch wafer.
"Dry Etching for High Aspect Ratio Silicon Fins,"
Journal of the Microelectronic Engineering Conference: Vol. 20
, Article 4.
Available at: https://scholarworks.rit.edu/ritamec/vol20/iss1/4