A Fortran Coded Design Rule Checker was written to analyze the output file of the RIT Integrated Circuit Editor (ICE) program. The design rules for the RIT 4LEVELPMOS process have been successfully implemented for a die size of 1900 by 1900 square micrometers.
Conrad, Carl E.
"Automated Design Rule Checking,"
Journal of the Microelectronic Engineering Conference: Vol. 2
, Article 7.
Available at: https://scholarworks.rit.edu/ritamec/vol2/iss1/7