Redesign of an Eight-Bit, ECL DAC to Facilitate Speed and Functionality Testing of a BI-CMOS Process

Authors

William A. McGee

Publication Date

1988

Document Type

Paper

Abstract

The redesign and layout of a clocked eight-bit digital to analog converter using emitter coupled logic is examined based on testing of the original circuit, simulation of ground node resistance and pinout compatibility to a produced part. The completed layout is subjectively compared to the original circuit design. Production and evaluation is pending at this time.

Recommended Citation

McGee, William A. (1988) "Redesign of an Eight-Bit, ECL DAC to Facilitate Speed and Functionality Testing of a BI-CMOS Process," Journal of the Microelectronic Engineering Conference: Vol. 2: Iss. 1, Article 25.
Available at: https://repository.rit.edu/ritamec/vol2/iss1/25