This project dealt with the design of a 4-bit PMOS parallel comparator analog-to-digital converter. Using a predesigned comparator circuit, the rest of the logic was completed. Circuit analysis was performed using SPICE simulation. Circuit layout was done using integrated Circuit Editor (ICE). The PMOS process consists of four masking levels; diffusion, thin oxide, contact cuts, and metal.
"Design of a 4-Bit PMOS Parallel Comparator A/D Converter,"
Journal of the Microelectronic Engineering Conference: Vol. 2
, Article 14.
Available at: https://scholarworks.rit.edu/ritamec/vol2/iss1/14