Device characteristics are reported on Hf02 gate dielectrics deposited by atomic layer deposition (ALD), and jet vapor deposition (JVD) on strained-Si and bulk Si samples. Capacitance-Voltage (CV) analysis of samples shows comparable interface charge levels between strained-Si and bulk Si samples. A flat band shift of -0.5V was noted between the strained-Si and bulk Si for the JVD samples.
"Capacitance-Voltage Analysis of High-? Dielectric on Strained Silicon,"
Journal of the Microelectronic Engineering Conference: Vol. 14
, Article 5.
Available at: https://scholarworks.rit.edu/ritamec/vol14/iss1/5