The objective of this investigation was to characterize oxides grown on the sidewalls of etched silicon profiles. Conventional CMOS process technologies were used to fabricate vertical sidewall capacitors in addition to planar ones. Sidewall oxidation is a cornerstone in the development of non-planar CMOS devices such as the finFET and Vertical MOSFETs. The quality of this oxide is extremely important, even more so as devices are scaled such that oxide thicknesses are on the order of a few atomic layers. In order to obtain insight into the characteristics of these emerging devices, the effects of a non-planar gate oxidation must be completely characterized. For this study optimum process conditions have been identified based on anisotropy of the silicon etch, repeatability, and the ability to extract the required information. Capacitance-voltage (CV) and currentvoltage (IV) characterizations have been performed to electrically characterize the oxide as well as the associated oxide charges. Cross sectional SEM analysis was carried out to investigate the structural integrity of the siliconoxide interface.
Tabakman, Keith H.
"Gate Oxide Characterizations for Non-Planar CMOS,"
Journal of the Microelectronic Engineering Conference: Vol. 13
, Article 20.
Available at: https://scholarworks.rit.edu/ritamec/vol13/iss1/20