Conventional planar CMOS scaling is able to achieve the traditional 17% performance gain for generation to generation. Planar CMOS scaling will soon encounter a “red-zone” at 65nm node or lower as we proceed towards the road map. As a result, the industry is likely to adopt a non-planar, fully depleted structure of various geometries including finFET, double-gate planar MOSFETs and vertical MOSFETs that are being investigated. This study focuses on Silvaco simulation and modeling of vertical P-type MOSFETs. The goal of this project was to determine whether Silvaco adequately, models degenerate doping levels (e.g. delta doped region) to minimize the antipunch through effect in short channeling. Preliminary results show that the mesh sizing in the localized highly doped regions is critical for successful simulation. Specifically it is important to generate a localized mesh of approximately 10 points per Debye length. Results indicate the Silvaco software in not able incorporate exact modeling for delta-doped region.
"Simulation and Modeling of a Vertical PMOS Transistor,"
Journal of the Microelectronic Engineering Conference: Vol. 13
, Article 16.
Available at: https://scholarworks.rit.edu/ritamec/vol13/iss1/16