The motivation in creation of the Strongarm process flow was to create a robust “enabling” process that was easy to manufacture. Optimum process conditions have been determined through extensive SUPREM simulation. Electrical examination using ATLAS software allowed for parameter extraction of the computer-generated devices. Modeling the extracted parameters with standard device physics equations allowed for a SPICE level-2 analysis that could be verified through electrical testing of actual fabricated devices. The technology was designed for a two micron, twin-well process incorporating a 4Onm gate oxide and an N+ poly gate. Source and drain implants are at 2E15 cm2, and a unique NMOS VT adjustment is used that occurs during channel stop implant. The manufacturability of the technology was observed through the successful fabrication and verification of two initial lots in the Rochester Institute of Technology (RIT) Semiconductor and Microsystems Fabrication Laboratory (SMFL).
Hebding, Jeremiah L.
"Process Design, Development, Fabrication and Verification of a CMOS Technology for RIT,"
Journal of the Microelectronic Engineering Conference: Vol. 13
, Article 1.
Available at: https://scholarworks.rit.edu/ritamec/vol13/iss1/1