Applying chemical mechanical planarization techniques to form the gate for a Cu/Ti/SiO2/Si capacitor stack has shown to be a viable alternative to conventional etching techniques used in the fabrication of MOS devices. Furthermore, it is reported that CMP does not compromise the integrity of the dielectric nor does it have an adverse affect on device performance.
"Copper Gate MOS Capacitors Utilizing Chemical-Mechanical Planarization,"
Journal of the Microelectronic Engineering Conference: Vol. 12:
1, Article 11.
Available at: https://scholarworks.rit.edu/ritamec/vol12/iss1/11