Shallow trench isolation (STI) planarized with chemical mechanical polishing (CMP) has replaced local oxidation of silicon (LOCOS) as the conventional isolation technique for sub-micron devices. STI increases transistor-packing density, allowing for more functionality and speed per unit area. STI offer superior latch-up immunity, smaller channel-width encroachment and better planarity. The implementation and feasibility of STI has been examined for device fabrication at RIT previously. The process utilized was etching of shallow trenches using SF6-02 dry chemistry and trench fill by TEOS (tetraethylorthosilicate) oxide deposition. The etch chemistry used did not yield anisotropic etching and appreciable undercutting was observed. In the present study, STI process used includes 60 nm of thermal pad oxide and 160 nm of LPCVD nitride as the hard mask. To create the shallow trenches, Si is etched using SF6-CHF3 chemistry for dry etching. The objective is to etch the trenches of depth — 0.5 μm - 0.8 μm deep without undercutting and with high selectivity on resist. A series of experiments have been done to study the Si trench etching using SF6-CHF3 chemistry in the DryTek Quad tool by varying process parameters. The results will be presented at the conference.
Reece, Patrick W.
"Dry Etch of Shadow Trench Isolation,"
Journal of the Microelectronic Engineering Conference: Vol. 11
, Article 8.
Available at: https://scholarworks.rit.edu/ritamec/vol11/iss1/8